Frequency synthesizer apparatus and methods for improving capacitor code search accuracy using lsb modulation

ABSTRACT

A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 61/667,390, titled “Frequency Synthesizer Apparatus and Methods forImproving Lock Time With Overlapping Coarse and Fine Tuning CapacitorArrays,” filed Jul. 2, 2012, which is hereby incorporated by referencein its entirety.

TECHNICAL FIELD

The disclosure herein relates generally to frequency synthesizers andassociated methods, and more particularly to synthesizers having tunablecapacitor arrays.

BACKGROUND OF RELATED ART

Frequency synthesizers provide a way to adjust and control a frequencyof a periodic signal, such as a clock. Synthesizers with wide tuningranges often employ inductor-capacitor (LC) circuits having adjustableparameters, such as an adjustable capacitance. The capacitance may begenerated by a capacitor array that exhibits a desired capacitance inresponse to an N-bit codeword. Typically, each possible codeword isassociated with a range of oscillator frequencies. Thus, a 3-bitcodeword may have 8 possible sequences, with each possible sequencecorresponding to a sub-range of desired frequencies. Selection of adesired frequency is thus dependent on selection of a proper codeword.

To estimate the appropriate capacitor codeword corresponding to adesired frequency setting, conventional methods of frequency synthesisoften employ binary search techniques. One conventional binary searchalgorithm begins by activating the Nth bit of a given capacitor array,often referred to as the most-significant-bit (MSB). The value of theresulting capacitance is used in an LC circuit for the synthesizer, andthe frequency determined via an edge counter. The state of the bit isthen determined based on the value of the count, with the frequencygenerally varying in an inversely proportional manner to thecapacitance.

In some situations, especially for voltage-controlled-oscillator (VCO)applications, it may be desirable to reduce a gain associated with theVCO. This often increases the resolution and number of bits of thecapacitor array. For applications where the number of bits increases,problems relating to errors in frequency estimations may arise.Generally, allowable error in the VCO frequency estimation is inverselyproportional to 2^(N). By increasing the number of bits in the capacitorarray, such as by 1, the frequency estimation time doubles. So when thenumber of bits is increased from N to N+1, the total capacitor searchtime increases by:

(N+1)2^(N+1) /N2^(N)=2(N+1)/N

Therefore, the capacitor search time increases exponentially with thenumber of bits in the VCO capacitor codeword. For fast channel switchingand stringent locking time requirements, faster methods for estimating amore accurate capacitor codeword are desirable.

SUMMARY

Embodiments of frequency synthesizers are presented herein. In oneembodiment, a frequency synthesizer is disclosed that includes anoscillator to generate a signal of a controllable frequency. Thefrequency synthesizer also includes a counter having an input to receivethe signal and to generate a count of a number of periods of the signalwithin an enabled timing interval. A state machine controls a frequencysearch of a capacitor codeword associated with the oscillator. Thecapacitor codeword corresponds to a frequency of the signal. The statemachine generates an enable signal to define the enabled timinginterval. Gating logic is disposed between the state machine and thecounter to re-generate the enable signal proximate the counter. Thegating logic is coupled to the oscillator to selectively pass the signalto the counter.

In a further embodiment, a frequency synthesizer is disclosed thatincludes an oscillator having an output to deliver a signal of acontrollable frequency. The oscillator includes a capacitor bankresponsive to a multi-bit control signal to exhibit a capacitance. Theoscillator output frequency is based on the capacitance. Control logicgenerates the multi-bit control signal and determines each bit of themulti-bit control signal through a binary search step and a modulationof a least-significant-bit (LSB) of the multi-bit control signal. TheLSB modulation, combined with the binary search for each bit, results ina higher accuracy frequency estimation.

In one embodiment, an LSB modulation method may be employed to reduce amaximum estimation error. The method comprises setting a target signalfrequency, then searching for a multi-bit capacitor codewordcorresponding to the desired frequency. The searching includesevaluating each bit during respective portions of a time interval.During a first portion of the time interval, a first value is generatedthat is attributable to the current bit and any other previouslydetermined bits. During a second portion of the time interval, aleast-significant-bit (LSB) of the multi-bit capacitor codeword ismodulated to generate a second value attributable to the currentlyevaluated bit and the other previously determined bits, and themodulated LSB. A state of the currently evaluated bit is then determinedbased on a combination of the first and second values. For one specificembodiment, when the LSB is evaluated, a final step of incrementing theLSB of the final codeword is performed.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments are illustrated by way of example and are notintended to be limited by the figures of the accompanying drawings.

FIG. 1 illustrates one embodiment of a frequency synthesizer circuit.

FIG. 2A illustrates one embodiment of the capacitor array of FIG. 1.

FIG. 2B illustrates a further embodiment of the capacitor array of FIG.1.

FIG. 3 illustrates further detail of one embodiment of the capacitorcontrol logic of FIG. 1.

FIG. 4 illustrates a timing chart that overlays respective oscillatoroutput and enable waveforms to show how the counting window is defined.

FIG. 5 illustrates further detail relating to the enable countgeneration circuit of FIG. 3.

FIG. 6 illustrates a timing chart that shows an enable count waveformgenerated by the circuit of FIG. 5 compared to an enable count togglewaveform.

FIG. 7 illustrates a flowchart for one embodiment of an LSB modulationsearch method used to reduce maximum frequency estimation error during abinary search.

FIG. 8 illustrates a flowchart for a further embodiment of a capacitorcodeword search method that employs an interpolation technique.

FIG. 9 illustrates a graphical depiction of an interpolation operationconsistent with the flowchart of FIG. 8 to estimate a fine capacitorarray codeword.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forthsuch as examples of specific components, circuits, and processes toprovide a thorough understanding of the present disclosure. Also, in thefollowing description and for purposes of explanation, specificnomenclature is set forth to provide a thorough understanding of thepresent embodiments. However, it will be apparent to one skilled in theart that these specific details may not be required to practice thepresent embodiments. In other instances, well-known circuits and devicesare shown in block diagram form to avoid obscuring the presentdisclosure. The term “coupled” as used herein means connected directlyto or connected through one or more intervening components or circuits.Any of the signals provided over various buses described herein may betime-multiplexed with other signals and provided over one or more commonbuses. Additionally, the interconnection between circuit elements orsoftware blocks may be shown as buses or as single signal lines. Each ofthe buses may alternatively be a single signal line, and each of thesingle signal lines may alternatively be buses, and a single line or busmight represent any one or more of a myriad of physical or logicalmechanisms for communication between components. The present embodimentsare not to be construed as limited to specific examples described hereinbut rather to include within their scopes all embodiments defined by theappended claims.

More specifically, and referring now to FIG. 1, one embodiment of afrequency synthesizer circuit is shown, generally designated 100, thatemploys an oscillator 102 coupled to capacitor control logic 104. Theoscillator 102 includes oscillator logic 106 that may take the form of avoltage-controlled oscillator (VCO). A VCO can generally vary a periodicoutput signal in response to an input voltage. The oscillator 102includes a capacitive impedance circuit, such as a capacitor array orbank 108. In some embodiments, the capacitor bank 108 may be coupled toan inductive impedance L to form a tunable LC circuit. The combinedinductive and capacitive circuits enable the oscillator 102 to generatean output waveform OUT of a controllable frequency. Other impedances mayalso be employed, such as resistive impedances in combination with theLC circuit, depending on the application and desired electricalparameters.

For one embodiment, shown in FIG. 2A, the capacitor bank 108 may berepresented as a multi-bit coarse array 202 of equally-spaced capacitorcircuits, where the aggregate number of control bits define a codedsequence, or codeword, to uniquely identify each coarse capacitorcircuit. In this context, “coarse” refers to a relatively wide range infrequencies associated with each possible codeword. Thus, for a coarsearray defined by an eight-level capacitor bank, each capacitance levelmay be uniquely identified by a 3-bit codeword, as shown by the bitsequences 0-0-0 through 1-1-1, in FIG. 2A. A fine array of capacitorcircuits 204 may also be employed to improve the resolution of thecapacitor bank. As an example, a number N of finely-spaced bits may beused that together span a frequency range defined by aleast-significant-bit (LSB) of the coarse array. Thus, a given estimatedcodeword may have a coarse capacitor array component (a coarsesub-word), and a fine capacitor array component (a fine sub-codeword).For the specific example shown, each capacitor circuit, when activated,may exhibit an amount of capacitance that corresponds to the oscillatoroutput frequency in an inversely proportional manner.

Referring now to FIG. 2B, in a further embodiment, the capacitor bank108 may take the form of a coarse capacitor array 206 similar to thatdescribed above relating to FIG. 2A. A fine capacitor array 208 may alsobe employed that spans a frequency range that not only fits within arange corresponding to a coarse bit of the coarse capacitor array 206,but overlaps partially into a range defined by a second capacitorcircuit such as that indicated by the label “Overlap” in FIG. 2B. Theoverlap forms a redundant amount of capacitance that may be useful insome situations, as more fully described below.

Referring back to FIG. 1, to select the proper level of capacitancecorresponding to a desired target oscillator frequency, the capacitorcontrol logic 104 evaluates an initial capacitor control signal CTL thatprovides an initial capacitor estimate to achieve the desired targetfrequency. The capacitor control logic 104 manages a search process,more fully described below, to tune the capacitor bank 108 such that itexhibits a capacitance that results in an oscillator output that hasimproved accuracy in the value of the output frequency.

Since the capacitor bank or array 108 has a finite number of levelscorresponding to each possible capacitor codeword, a range of targetfrequencies is assigned to each possible codeword. Thus, an error mayexist between a desired target frequency, and the actual frequencyexhibited by the capacitor codeword assigned to the range of frequenciesthat includes the target frequency. This is known as quantization error.Apparatus and methods described herein seek to minimize thatquantization error.

FIG. 3 illustrates further detail of one embodiment of the capacitorcontrol logic 104, including gating logic 306, a frequency counter 304,and a state machine 308. The gating logic 306 in one form includes an“AND” gate that has a first input to receive the oscillator output OUTfrom the oscillator 102, and a second input to receive an enable signalENABLE. The enable signal ENABLE is generated by the state machine 308to define a time interval for counting by the frequency counter 304. Thecount value divided by the time interval generally corresponds to theoscillator frequency.

An example of the relative timing between the oscillator output OUT andthe enable signal ENABLE is shown in FIG. 4. Rising edges 402 of theoscillator output OUT are represented by upwardly pointing arrowssuperimposed on the signal waveform. When the enable signal ENABLE ishigh, the oscillator output signal OUT is regenerated by the gatinglogic 306 and fed to the frequency counter 304, where a count is carriedout of the number of rising edges 402 detected during the interval oftime defined by the enable signal ENABLE, such as interval 404.

Referring back to FIG. 3, the frequency counter 304 feeds its output tothe state machine 308, which compares the generated count value to anexpected value. The expected value may be based on the control signalCTL that specifies the target frequency of the oscillator output signalOUT. In one specific embodiment, the frequency counter is a synchronousdevice and may take the form of a ripple counter. This helps minimizemetastability issues that may arise from gating the periodic oscillatoroutput into the synchronous frequency counter.

Generally, in one embodiment, the state machine 308 may operate inaccordance with an LSB-modulated capacitor code search process,described below, to evaluate the count value and generate the adjustmentcontrol signal ADJ for tuning the capacitor bank 108 to achieve thetarget frequency. In another embodiment, the state machine may alsosupport an interpolation search mode, also described below, forestimating fine capacitor array sub-codewords. Selecting between anLSB-modulated binary search mode or an interpolation mode may be madevia a programmed value stored in a mode register 310. The state machine308 may also periodically generate a reset signal RESET to cause thefrequency counter to start counting from a preselected reference countvalue, such as “0.”

In one embodiment, the state machine 308 includes circuitry that ispositioned electrically remote or relatively distant from the gatinglogic 306. In some situations, parasitics and/or other forms ofelectrical interference may cause undesirable distortion in the enablesignal ENABLE as it propagates from the state machine 308 to the gatinglogic 306. As a result, a rising edge of the enable signal ENABLE, whichmay often be used to define the start of a count window, may have adifferent rise time than the falling edge, which often defines the endof a count window. In extreme cases, the distortion may createinaccuracies in defining the enable interval or counting window 402(FIG. 4) for generating the oscillator output count.

To address potential distortion acting on the enable signal ENABLE, FIG.5 illustrates additional logic, such as a flip-flop 502, that may bedisposed between the state machine 308 and the gating logic 306. FIG. 5illustrates one embodiment of the flip-flop 502, with a toggling enablesignal TE generated by the state machine 308 and fed to a clock input CKof the flip-flop. The flip-flop 502 includes an output Q that couples toa data input D via an inverter gate 504. The flip-flop 502 includes areset port R to reset the output Q to a default state. The reset port isresponsive to the same reset signal RESET that is fed to the frequencycounter 304 to reset the count.

FIG. 6 illustrates the resulting timing, where a rising edge 602 of aninitial pulse 604 of the toggling enable signal TE is received by the CKinput of the flip-flop 502 to generate one edge of a clean andundistorted enable signal ENABLE, at 606. A second pulse 608 of thetoggling enable signal TE is received at the flip-flop 502 to generate aclosing edge 610 of the enable signal ENABLE. Since both rising edges ofthe toggling enable signal TE are used to generate the enable signalENABLE, and since both are affected by parasitics in the same manner,the enable signal ENABLE, which is generated locally by flip-flop 402,may be generated with higher timing accuracy.

For one embodiment, the frequency synthesizer circuit 100 (FIG. 1)estimates a capacitor codeword for the capacitor bank 108 using a uniquesearch scheme that modulates the LSB while each bit of the codeword isbeing determined. This enables the proper codeword to be determined withless error than is often attributable to other techniques. For purposesof clarity, the method is described in the context of determining thecoarse capacitor array bits. A similar search scheme may be employed todetermine the fine array bits. For embodiments where a fine array isemployed, the LSB is the LSB of the fine array. Alternatively, aninterpolation method may be used to determine the fine array code asexplained below.

FIG. 7 sets out a flowchart that may be employed in the LSB modulatedsearch method, generally designated 700. For VCO applications, themethod may begin with the oscillator logic 106 receiving a change in aninput voltage, thereby representing a frequency change to a desiredtarget frequency, at 702 (and also illustrated in FIG. 1). The desiredtarget frequency corresponds to a specific control signal value CTL,which is fed to both the capacitor control logic 104. Other applicationsmay receive a different form of signal indicating a desired frequencychange.

With the control signal CTL received, the capacitor bank 108 switches-ina capacitance corresponding to the most-significant-bit MSB of thecapacitor codeword, at 704. As a specific example, for a 3-bit codeword,and a target frequency set just under the codeword value “1-1-0” (shownin FIG. 1), the initial search codeword begins with a sequence of“1-0-0.” For each evaluated codeword bit, the state machine 308 definesthe window for counting edges of the resulting periodic waveform fromthe applied codeword. For this example, during a first half of the countwindow, a capacitance corresponding to the initial codeword “1-0-0” willbe provided for the oscillator logic 106, and the rising edges counted,at 706. However, for the second half of the count window, the capacitorarray LSB of the initial codeword is incremented by 1, to a sequence of“1-0-1”, at 708, and the rising edges counted based on a capacitancecorresponding to the sequence “1-0-1”, at 710.

At the end of the count window, the total count value is determined, at712, from the counts taken during the first half and second half of thecount window and represents an actual frequency value. The total countvalue may then be compared to an expected total count value, at 714. Ifthe actual value is higher than the expected value from a determinationmade at 716, then the capacitance corresponding to the MSB is too low,and the MSB value is set to a “1”, at 718. This corresponds to aspecific embodiment where an increasing capacitor codeword representsincreasing capacitance, which is inversely proportional to frequency.Other embodiments may be configured such that an increasing capacitorcodeword corresponds to decreasing capacitance. In such cases, thedecision for the bit is evaluated in an opposite manner. If the actualcount value is lower than the expected value, then the MSB is set to a“0”, at 720.

Thus, for each bit, the total count value generally corresponds to anaverage frequency value based on a capacitance from the codeword set bythe evaluated MSB, and the capacitance resulting from the modulation orincrementing of the LSB to the codeword.

Further referring to FIG. 7, once the MSB is evaluated, a determinationof whether the bit was the LSB is made, at 722. If the bit is not theLSB, then the next most significant bit may be selected for evaluation,at 724, and steps 704-720 repeated for that bit. So to continue with thespecific example set out above, with the MSB bit determined to be a “1”,the middle bit may then be evaluated by initially switching-in acapacitance corresponding to a codeword value of “1-1-0.” TheLSB-modulated codeword results in a sequence of “1-1-1.” During thecount evaluation, the total count may be determined to be too low,resulting from a capacitance that is too high. Thus, the middle bit maybe set to a “0.”

When the actual LSB undergoes its evaluation, the same steps 704-720 maybe followed. Thus, with the first two of the bits determined to be “1”and “0”, the LSB may be initially set to a “1” state, with the overallcodeword at “1-0-1.” The LSB-modulated value is “1-1-0”, which isapplied during the second half of the count window. The determined statefor the LSB may result in a “1”, and a sub-final codeword may be“1-0-1.” However, unlike the previously determined bits, when the LSB isevaluated, the final codeword value may be altered by incrementing theLSB by 1, at 726 (FIG. 7). Thus, for the specific example presented, thefinal codeword may be “1-1-0.”

An advantage to modulating the LSB for each of the bit evaluation searchsteps is that a maximum error between a desired target frequency, andthe search capacitor codeword frequency may be reduced between adjacentcodeword bits. Standard binary search methods, on the other hand, mayresult in maximum errors that approach an entire range of frequenciesspanning the LSB. Thus, the LSB modulation search method described aboveprovides a more accurate method of estimating the capacitor codeword,often resulting in a maximum error that is significantly less than themaximum error typically associated with binary-only search methods.

As noted above, for embodiments that employ dual capacitor arrays (bothcoarse and fine arrays), the fine capacitor array bits may be estimatedin the same manner as the coarse array bits (LSB modulation). In someembodiments, however, the search time for the fine array may be improvedusing an interpolation method, such as that described below.

FIG. 8 illustrates a flowchart for one embodiment of an interpolationmethod, generally designated 800, to estimate a capacitor codeword for afine capacitor array. Rather than searching for each bit sequentially,the method generally involves identifying at least two points, andrelying on the linearity of the relationship between fine arraysub-capacitor codeword values and frequency to identify a sub-codewordfor the fine capacitor array bits that correlates with a desired targetfrequency.

Further referring to FIG. 8, one embodiment of an interpolation methodbegins by taking an accurate frequency measurement of a given bit in thefine capacitor array, such as a bit corresponding to a minimal or “zero”range for the fine capacitor array, at 802. The measurement may becarried out by counting the pulses generated by a periodic waveformresulting from the “zero” capacitance level. A similar measurement maybe made, at 804, for a second value associated with the fine capacitorarray, such as a bit corresponding to a maximum or “full-scale” rangefor the fine capacitor array. Selection of the zero and full-scalepoints are exemplary only, and other points within the fine capacitorarray may be selected. Also, the order in which the points may bemeasured are arbitrary, such that a full-scale value may be measuredbefore a zero value.

Once the two points have been measured, the linear relationship, orslope, between the measured frequencies and the correspondingsub-codewords may be determined, at 806. The relationship may then beapplied, at 808, to interpolate between the two points to associate thesub-codeword values to corresponding frequency values. The estimatedsub-codeword for the target frequency is then determined as thesub-codeword associated with a frequency closest to the desired targetfrequency, at 810. Note that the desired target frequency is a frequencyvalue that supplements the coarse array value, thus providing finerresolution for the frequency synthesizer.

To more clearly illustrate the interpolation approach to estimating afine capacitor array sub-codeword, FIG. 9 illustrates a graph ofoscillator frequency as a function of capacitor sub-codeword values. Asan example, a first measured point representing a “zero” is illustratedat 902, while a representative “full-scale” point is illustrated at 904.The interpolated slope is represented by the line at 906. Theintersection of the line with the target frequency, at 908, is where anideal capacitor sub-codeword value would lie, assuming a very highresolution. The closest sub-codeword to the intersection represents theestimated sub-codeword for the fine capacitor array.

For one embodiment, the capacitor control logic 104 (FIG. 1) may supportmultiple modes of operation that allow the frequency synthesizer 100 tosearch for capacitor array codewords in a variety of ways to optimallyrespond to a variety of situations. As an example, an estimated codewordfor a given coarse array may be determined via a binary technique or theLSB-modulated method described herein, and a fine capacitor arraysub-codeword searched via either a second LSB-modulated search sequenceor an interpolation-based method. The programmable mode bits describedearlier that are stored in the mode register 310 (FIG. 3) generallyprovide a flexible and convenient way to determine which method toemploy for capacitor codeword searching.

Those skilled in the art will appreciate the benefits and advantagesafforded by the embodiments described herein. By utilizing a synthesizercircuit and associated methods to estimate a target frequency with anLSB modulation scheme, a resulting capacitor code may be determined thatexhibits a maximum error that is significantly less than the maximumerror associated with other methods. Moreover, the apparatus and searchmethods described herein minimize search time while improving accuracy.

In the foregoing specification, the present embodiments have beendescribed with reference to specific exemplary embodiments thereof. Itwill, however, be evident that various modifications and changes may bemade thereto without departing from the scope of the disclosure as setforth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. A frequency synthesizer comprising: an oscillatorto generate a signal of a controllable frequency; a counter having aninput to receive the signal and to generate a count of a number ofperiods of the signal within an enabled timing interval; a state machineto control a frequency search of a capacitor code associated with theoscillator, the capacitor code corresponding to a frequency of thesignal, the state machine to generate an enable signal to define theenabled timing interval; and gating logic disposed between the statemachine and the counter to re-generate the enable signal proximate thecounter, the gating logic coupled to the oscillator to selectively passthe signal to the counter.
 2. The frequency synthesizer of claim 1wherein the oscillator comprises a voltage-controlled oscillator (VCO).3. The frequency synthesizer of claim 1, wherein the oscillator includesa capacitor bank responsive to the capacitor code to exhibit acapacitance corresponding to the frequency of the signal.
 4. Thefrequency synthesizer of claim 3, wherein the capacitor bank includesmultiple equally spaced-apart levels to define a coarse array, thecapacitor code corresponding to one of the levels.
 5. The frequencysynthesizer of claim 1, wherein the counter comprises a ripple counter.6. The frequency synthesizer according to claim 4, further comprising: afine array of multiple equally spaced-apart levels within one of thelevels of the coarse array.
 7. The frequency synthesizer according toclaim 4, further comprising: a fine array of multiple equallyspaced-apart levels that overlap two of the levels of the coarse array.8. A frequency synthesizer comprising: an oscillator including an outputto deliver a signal of a controllable frequency, a capacitor bankresponsive to a multi-bit control signal to exhibit a capacitance, theoscillator output frequency based on the capacitance; and control logicto generate the multi-bit control signal, each bit of the multi-bitcontrol signal determined through a binary search and a modulation of aleast-significant-bit (LSB) of the multi-bit control signal.
 9. Thefrequency synthesizer according to claim 8, wherein the oscillatorcomprises a voltage-controlled-oscillator (VCO).
 10. The frequencysynthesizer according to claim 8 wherein the control logic comprises: acounter having an input to receive the signal and to generate a count ofa number of periods of the signal within an enabled timing interval; anda state machine to control a frequency search of the multi-bit controlsignal associated with the signal, the state machine to generate anenable signal to define the enabled timing interval.
 11. The frequencysynthesizer according to claim 10 and further comprising: gating logicdisposed between the state machine and the counter to re-generate theenable signal proximate the counter, the gating logic coupled to theoscillator to selectively pass the signal to the counter.
 12. Thefrequency synthesizer according to claim 8 wherein the capacitor bankincludes a coarse array of multiple equally spaced-apart levels, themulti-bit control signal comprising a capacitor code corresponding toone of the levels.
 13. The frequency synthesizer according to claim 12,further comprising: a fine array of multiple equally spaced-apart levelswithin one of the levels of the coarse array.
 14. The frequencysynthesizer according to claim 12, further comprising: a fine array ofmultiple equally spaced-apart levels within one of the levels of thecoarse array and overlapping into a second level of the coarse array.15. A method of synthesizing a signal of a desired frequency from aninductor-capacitor (LC) oscillator, the method comprising: setting atarget signal frequency; searching for a multi-bit capacitor codewordcorresponding to the desired frequency, the searching includingevaluating each bit of the multiple bits by during a first portion of atime interval, generating a first value attributable to the bit and anyother previously determined bits, during a second portion of the timeinterval, incrementing a least-significant-bit (LSB) of the multi-bitcapacitor codeword and generating a second value attributable to theevaluated bit and any other previously determined bits, and theincremented LSB, and determining a state of the evaluated bit based on acombination of the first and second values.
 16. The method according toclaim 15, further comprising: counting periods of a first signal togenerate a first count; counting periods of a second signal to generatea second count; summing the first and second counts; and determining thestate of the evaluated bit based on a frequency corresponding to thesummed first and second counts.
 17. The method according to claim 16,wherein a maximum error between the desired frequency and the targetsignal frequency is half of a frequency range corresponding to one ofthe multiple bits.
 18. The method according to claim 16, whereindetermining the state of the evaluated bit comprises: comparing thesummed first and second counts to an expected value; and selecting thestate based on the comparison.
 19. The method according to claim 18,wherein after evaluating a state of the last of the N bits, the methodfurther comprises: incrementing the LSB.
 20. The method according toclaim 19, wherein the last bit comprises the LSB.
 21. A frequencysynthesizer comprising: means for setting a target signal frequency;means for searching for a multi-bit capacitor codeword corresponding toa desired frequency, the means for searching including means forevaluating each bit of the multiple bits by during a first portion of atime interval, generating a first value attributable to the bit and anyother previously determined bits, during a second portion of the timeinterval, incrementing a least-significant-bit (LSB) of the multi-bitcapacitor codeword and generating a second value attributable to theevaluated bit and any other previously determined bits, and theincremented LSB, and means for determining a state of the evaluated bitbased on a combination of the first and second values.
 22. A method ofsynthesizing a signal of a desired frequency from an inductor-capacitor(LC) oscillator, the method comprising: setting a target signalfrequency; in a first mode searching for a multi-bit capacitor codewordcorresponding to the desired frequency using an LSB-modulationtechnique; and in a second mode searching for the multi-bit capacitorcodeword corresponding to the desired frequency using a binary searchtechnique.
 23. The method of claim 22, and further comprising:programmably selecting between the first and second modes.